1. Field of the Invention
The present invention relates to a high-frequency switch and an electronic device using the same, and particularly to a high-frequency switch used for switching millimeter bandwidth signals and an electronic device using the same.
2. Description of the Related Art
Generally, switches using PIN diodes are used for switching millimeter bandwidth signals and so forth. Switches using FETs may be used for relatively low frequencies, such as switches which use the lines themselves where high-frequency signals pass, as the drain and source of the FETs. Specific examples are disclosed in Japanese Unexamined Patent Application Publication No. 6-232601, Japanese Unexamined Patent Application Publication No. 10-41404, Japanese Unexamined Patent Application Publication No. 2000-294568, Japanese Unexamined Patent Application Publication No. 2000-332502, and so forth.
Japanese Unexamined Patent Application Publication No. 6-232601 (first conventional example) discloses a high-frequency switch which uses a part of the signal lines as an FET by dividing a signal line into multiple drain electrodes by multiple slits traversing the signal line in the width direction thereof, and also forming source electrodes and gate electrodes (lines) extending in the width direction of the signal line in the same manner as with the slits (e.g., FIG. 13 in the Publication). The drain electrodes are each connected by metal lines. Also, inductance devices having parallel resonance with the off capacitance of the FET at the signal frequency are connected between the drains and sources of the FETs.
In the first conventional example, the signal line itself is constantly in a DC conducting state, including the portions where the FET is formed. Upon the FET turning on, the impedance of the circuit connected between the signal line and ground is reduced to an almost short-circuit state. Consequently, a portion of the signal line is in a generally grounded state so the high-frequency signals are reflected, preventing conduction. Conversely, when the FET is off, the impedance at the frequency of the high-frequency signals of the circuit connected between the signal line and ground becomes infinite, due to the parallel resonance between the off capacitance of the FET and the inductance device. This means that nothing is connected to the signal line at the frequency of the high-frequency signals, so the high-frequency signals are conducted. Thus, switching operations are carried out.
Japanese Unexamined Patent Application Publication No. 10-41404 (second conventional example) discloses a high-frequency switch wherein, at a part of the signal line (functioning as a drain electrode), a ground electrode (functioning as a source electrode) is formed adjacent thereof in the longitudinal direction, and a gate electrode extending in the longitudinal direction of the signal line is formed in the gap therebetween (e.g., FIG. 6 in the Publication).
With the second conventional example, the part of the signal line acting as a drain acts simply as the signal line when the FET is off, so the signal line conducts the high-frequency signals. On the other hand, when the FET is off, the part of the signal line acting as the drain is connected to the ground electrode, so the part of the signal line is essentially grounded, so the high-frequency signals are reflected, and conduction is prevented.
Japanese Unexamined Patent Application Publication No. 2000-294568 (third conventional example) discloses a configuration with the same FET configurations as in the first conventional example (FIG. 8 in the Publication, no inductance device for parallel resonance), and with the drain, source, and gate of the FET extending in the line direction of the signal line with the same configuration (FIG. 1 in the Publication).
In the third conventional example as well, the same operations as with the second conventional example are performed, in that a part of the signal line essentially is grounded when the FET is on, thereby preventing conduction of high-frequency signals.
Japanese Unexamined Patent Application Publication No. 2000-332502 (fourth conventional example) discloses an arrangement wherein a ¼ wavelength stub is connected to the main line of the signal lines, and further wherein the tip of the stub is used as the drain electrode and the source electrode is grounded, thereby forming an FET (FIGS. 2 and 6 in the Publication). Turning the FET on and off operates the stub as a ¼ wavelength short stub and an open stub.
In the fourth conventional example as well, the stub serves as a ¼ wavelength open stub when the FET is off, and the same operation as with the second and third conventional examples is performed in that a part of the signal line essentially is grounded under the frequency of high-frequency signals, thereby preventing connection of high-frequency signals.
Now, with the first conventional example, there is the need to reduce the conduction resistance when the FET is on, and to that end, there is the need to increase the number of signal line divisions and increase the number of gate electrodes, so as to increase the total gate width of the FET. Increasing the total gate width necessitates a greater off capacitance of the FET, so there is the need to reduce the inductance value of the inductance device for parallel resonance, accordingly. However, there is a limit to how far the shape of the inductance device can be reduced with the same level of precision in inductance value. Further, the higher the signal frequency is, the smaller the inductance value needs to be, so there is the problem with this configuration that the higher the signal frequency is, the harder it is to use.
On the other hand, with the second conventional example, the above problem, wherein the higher the signal frequency is the harder the device is to use, does not occur since the resonance phenomenon is not used. However, with the first conventional example, the main line itself of the signal lines, where high-frequency signals flow when the FET is switched on, is the drain electrode of the FET. At least a part of the drain electrode is formed on a semiconductor activation layer, which means that part of the main line has been formed on a semiconductor activation layer. The high-frequency signals flow through the semiconductor activation layer as part of the line, but the semiconductor activation layer is a conductor with higher resistance than the drain electrode, meaning that the resistance of the main line is increased. Accordingly, with switches wherein the main line itself is the drain electrode for the FET as with the first conventional example, this arrangement is a factor in increasing insertion loss of the main line.
Also, the on resistance per increment length of the FET can be reduced by changing the cross-sectional structure of the FET, which is not necessarily easy. In the event that the on resistance per increment length cannot be changed, there is the need to increase the gate width of the FET in order to effect sufficient grounding of the main line when the FET is on. Increasing the gate width of the FET means extending the gate electrode in the longitudinal direction of the signal line, which in turn means that the drain electrode also becomes longer, resulting in an increased size of the switch in the longitudinal direction of the main line. The drain electrode is also the main line formed on the semiconductor activation layer where high-frequency signals are applied, and accordingly, the tendencies of increase in the above-described insertion loss of the main line are further accentuated.
Next, the third conventional example has been same basic configuration as with the first conventional example, and has the same problems.
Finally, with the fourth conventional example, the main line where the high-frequency signals flow is not the drain electrode, so there is no problem of increased insertion loss upon switching on. However, there is the need to lengthen the gate width of the FET to obtain grounding with sufficiently low resistance for the stub end. Lengthening the FET gate width increases the capacitance between the drain and source when the FET is off. This means that a great capacitance exists between the tip of the open stub and the ground with the FET is off. In the event that a great capacitance exists at the tip of the open stub, the resonance frequency of the open stub decreases, so the resonance frequency may be different from that when a short stub. Having different resonance frequencies for an open stub and short stub means that the switch cannot function normally, which is a great problem.